1. Field of the Invention
This invention relates to a novel, vertical gate, field effect transistor (FET), and more particularly, to an FET that has a very short channel length.
2. Description of the Prior Art
There have been a number of prior art proposals relating to FET structures with vertical gate geometries. In general, these proposals rely on a diffusion process to form the gate channel. Representative examples of this prior art include the following list of U.S. patents, each of which relates to a double diffusion MOS device.
U.S. Pat. No. 4,970,173 entitled "Method of Making High Voltage Vertical Field Effect Transistor with Improved Safe Operating Area"; U.S. Pat. No. 4,914,051 entitled "Method for Forming a Vertical Power DMOS Transistor with Small Signal Bipolar Transistor"; U.S. Pat. No. 4,983,535 entitled "Vertical DMOS Transistor Fabrication Process".
However, as will be appreciated by those skilled in the art, the dimensions of device layers deposited by silicon epitaxy are limited to values greater than the diffusion length of dopants out of the substrate, where these dimensions can be on the order of a micron under typical high-temperature processing conditions (T&gt;1000.degree. C.).
Thus, prior art proposals for manufacturing field effect transistors with a channel length on the order of 0.1 .mu.m have heretofor relied on the use of special process steps, such as electron-beam or X-ray lithography, in order to provide the required tolerances at this extremely small feature size. However, as will be appreciated by those skilled in the art, the use of such advanced process steps as electron-beam and X-ray increase the manufacturing cost of integrated circuits and increase the turnaround time of the manufacturing process where they must be used.